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Operating principle of internal modem
This device is a simplex link handling
a 1200 baud asynchronous datastream (1 start, 8data, 1stop).
Buffering in the transmit end handles TX startup timing requirements,
while the presence of sync codes in the transmitted bursts
prevents the receiver from outputting garbage in the presence
of noise. No error correction or retransmission of lost packets
is supported. To operate with proper +/-12V RS232 levels an
external buffer (such as a MAX232) will be needed
Physically the modem code resides in the
PIC microcontroller which controls the radio functions. The
modem uses the internal hardware serial port of the processor.
Operation: Serial interface
Both transmit and receive modems implement
a 32 byte software FIFO. At the transmit end this is used
to allow for the TX1M transmitter start up time (about 32ms),
while on receive it buffers arriving packets to the constant
output data rate. All timing and data formatting tasks are
handled by the software. The user need not worry about keying
the transmitter before sending data: the link is entirely
transparent.
For transmission across the link data is
formatted into packets, each comprising 3 bytes of data and
a sync code. If less than 3 bytes are in the transmit end
FIFO then a packet is still sent, but idle state replaces
the unused bytes. When the transmit end FIFO is completely
emptied, then the transmitter is keyed off .
Operation: Radio interface
Raw data is not fed to the radios. A coding
operation in the transmit software, and decoding in the receiver,
isolate the AC coupled, potentially noisy baseband radio environment
from the datastream.
The radio link is fed a continuous tone
by the modem. As in biphase codes, information is coded by
varying the duration consecutive half-cycles of this tone.
In our case half cycles of 500us (a long, or L) and 250us
(a short, or S) are used.
In idle (or 'preamble') state, a sequence
of Ls is sent (resembling a 1KHz tone).
A packet comprises the Synchronising (or
address) part : LSSSSSSSSSSSSL followed by the Data part,
made up of twelve Groups (of four half cycles duration). Each
Group encodes 2 data bits, so one byte is encoded by 4 Groups.
Although there are 16 possible states for
a four half cycle group (from SSSS to LLLL), only four of
the possible states are used for valid data:
All other possible group combinations (except LLLL) are void,
and result in the entire packet being rejected by the receiver
software as a noise artifact. Idle state tone (LLLL ....)
is decoded as null data, but does not void the packet, as
a packet containing less than 3 bytes still needs to be decoded.
The advantage of using the above coding
technique:
1.Ease of decoding: Unlike biphase, where
a bit is coded as either a long half cycle or a short cycle,
here all half cycles are detected separately.
2. Inherent error detection: Although only
14 sync/address 'bits' (halfcycles) are used, the following
48 'bits' (halfcycles) only code 24 real data bits, leading
to enhanced noise/error discrimination (the equivalent of
5 more sync bits).
3. Comparable spectral efficiency: For
a maximum transmitted baseband frequency of 2KHz, a 3 byte
packet is sent in 22ms. An equivalent biphase coded packet
(comprising 19 sync + 24 data + 3 null flags) at 2kbits/sec
takes 23ms
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