© Radiometrix Ltd

                                                                                              SP2-433-160

INTRODUCTION

The SP2 is a self-contained plug-on radio port which requires only a simple antenna, 5V supply and a byte-wide I/O port on a host microcontroller (or bi-directional PC port). The module provides all the RF circuits and processor intensive low level packet formatting and packet recovery functions required to inter-connect an number of microcontrollers in a radio network.

A data packet of 1 to 60 bytes downloaded by a Host microcontroller into the SP2's packet buffer is transmitted by the SP2's transceiver and will "appear" in the receive buffer of all the SP2's within radio range.

A data packet received by the SP2's transceiver is decoded, stored in a packet buffer and the Host microcontroller signalled that a valid packet is waiting to be uploaded.

Typical features include:

• SAW controlled FM transmitter and superhet receiver
• Reliable 50m in-building range, 200m open ground
• Complies with ETSI EN 300 220-3
• Complies with ETSI EN 301 489-3
• Single 5V supply @ < 25mA
• 160kbps half duplex
• Free format packets of 1 - 60 bytes
• Packet framing and error checking are user transparent
• Collision avoidance (Listen Before Transmit)
• Direct interface to 5V CMOS logic
• Power save mode

figure 1: SP2 + HOST µController
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figure 2: SP2 block diagram
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figure 3: physical dimensions
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1. FUNCTIONAL DESCRIPTION

On receipt of a packet downloaded by the Host, the SP2 will append to the packet: Preamble, start byte and a error check code. The packet is then coded for security and mark:space balance and transmitted through the BiM2 Transceiver as a 160kbps synchronous stream. One of four methods of collision avoidance (Listen Before TX) may be user selected.

When not in transmit mode, the SP2 continuously searches the radio noise for valid preamble. On detection of preamble, the SP2 synchronises to the in-coming data stream, decodes the data and validates the check sum. The Host is then signalled that a valid packet is waiting to be unloaded. The format of the packet is entirely of the users determination except the 1st byte (the Control Byte) which must specify the packet type (control or data) and the packet size. A valid received packet is presented back to the host in exactly the same form as it was given.

To preserve versatility, the SP2 does not generate routing information (i.e. source/ destination addresses) nor does it handshake packets. These network specific functions left for the Host to perform.

Additional features of the SP2 include extensive diagnostic/debug functions for evaluation and debugging of the radio and host driver software, a built in self test function and a sleep mode / wake-up mechanism which may be programmed to reduce the average current to less than 100µA. The operating parameters are fully programmable by the host and held in EEPROM, the host may also use the EEPROM as a general purpose non-volatile store for addresses , routing information etc.

1.1 OPERATING STATES

The SP2 is has four normal operating states:

• IDLE / SLEEP
• HOST TRANSFER
• TRANSMIT
• RECEIVE

IDLE/SLEEP
The IDLE state is the quiescent/rest state of the SP2. In IDLE the SP2 enables the receiver and continuously searches the radio noise for message preamble. If the power saving modes have been enabled the SP2 will pulse the receiver on, check for preamble and go back to SLEEP if nothing is found. The 'ON' time is 2.5ms, OFF time is programmable in the SP2's EEPROM and can vary between 22 ms and 181ms. The TX Request line from the Host is constantly monitored and will be acted upon if found active (low). A TX Request will immediately wake the SP2 up from SLEEP mode.

HOST TRANSFERS
If the host sets the TX Request line low a data transfer from the Host to the SP2 will be initiated. Similarly the SP2 will pull RX Request low when it requires to transfer data to the Host (this may polled or used to generate a Host interrupt ).

The transfer protocol is fully asynchronous, i.e. the host may service another interrupt and then continue with the SP2 transfer. It is desirable that all transfers are completed quickly since the radio transceiver is disabled until the Host <> SP2 transfer is completed. Typically a fast host can transfer a 60 byte packet to / from the SP2 in under 1ms.

TRANSMIT
On receipt of a data packet from the host, the SP2 will append to the packet - preamble, frame sync byte and an error check sum. The packet is then coded for mark:space balance and transmitted. A full 60 byte packet is transmitted in 6ms of TX air time (60 byte data @ 160kbps + 1.75ms preamble).

Collision avoidance (Listen Before Transmit) functions can be enabled to prevent loss of packets.

Data packets may be sent with either normal or extended preamble. Extended preamble is used if the remote SP2 is in power save mode. Extended preamble length can be changed in the EEPROM memory.

RECEIVE
On detection of preamble from the radio receiver, the SP2 will phase lock, decode and error check the incoming synchronous data stream and if successful. The data is then placed in a buffer and the RX Request line is pulled low to signal to the host that a valid packet awaits to be uploaded to the Host.
An in-coming data packet is presented back to the host in the same form as it was given.

2. THE HOST INTERFACE

2.1 SIGNALS

It is recommended that the SP2 be assigned to a byte wide bi-directional I/O port on the host processor. The port must be such that the 4 data lines can be direction controlled without affecting the 4 handshake line.

Notes:

1. The 4 Handshake lines are active low
2. The 4 Data lines true data
3. Logic levels are 5 volt CMOS, see electrical specifications
4. Input pins have a weak pull-up internally

RESET
The Reset signal, may either be driven by the host (recommended) or pulled up to Vcc via a suitable resistor (10kW). A reset aborts any transfers in progress and restarts the Packet Controller.

HOST DRIVEN RESET
Minimum low time: 1.0 µs, after reset is released (returned high). The host should allow a delay 1ms after reset for the SP2 to initialise ifself

During this delay the host must hold TXR high (unless DIAGNOSTIC MODES are required) and RXR signal should be ignored.

figure 4: Host to SP2 connection
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2.2 HOST TO SP2 DATA TRANSFER

Data is transferred between the SP2 and the HOST 4 bit's (nibbles) at a time using a fully asynchronous protocol. The nibbles are always sent in pairs to form a byte, the Least Significant Nibble (bits 0 to 3) is transferred first, followed by the Most Significant Nibble (bits 4 to 7). Two pairs of handshake lines, REQUEST & ACCEPT, control the flow of data in each direction:-

TX Request & TX Accept: control the flow from the HOST to the SP2 (download)
RX Request & RX Accept: control the flow from the SP2 to the HOST (upload)

A packet transferred between host and SP2 consists of between 1 and 61 bytes, the first byte of the packet is always the control byte.

There are two classes of HOST<—>SP2 transfers:

1. Data Packets: To the transmitter or from the receiver
2. Memory Access: To or from the SP2's memory

figure 5: SP2 to/from Host data transfer
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2.2.1 WRITE A BYTE TO SP2

The sequence for a byte transfer from the Host to the SP2 (i.e. TX download) is asynchronous and proceeds as follows:

1. HOST asserts TX Request line low to initiate transfer
2. Wait for SP2 to pull TX Accept low (i.e. request is accepted)
3. Set data lines to output and place LS nibble on the data lines
4. Negate TX Request (set to 1) to tell SP2 that data is present.
5. Wait for SP2 to negate TX Accept (i.e. data has been accepted)

Repeat steps 1-5 with MS nibble.

figure 6: TX download timing diagram
Click on the image for EXPANDED VIEW

Notes:

• The data bus must not be set to output until step 3. i.e. after the SP2 has accepted the request. The bus may be left as an output until the entire packet has been transferred to the SP2, it should then be set back to input (default state).
• The SP2's normal response time to the initial TX Request may be up to 1ms, thereafter, for the duration of the packet, the response will be fast.
• The SP2 will ignore a TX Request from the Host while it is receiving a packet from the radio. If the incoming packet fails it's error check the SP2 will respond to the TX Request as normal, i.e. the TX Accept from the SP2 will be delayed until the incoming packet has finished. If a valid packet is received this must be uploaded to the Host before the SP2 can respond to the Host's TX Request. Thus an RX Request will be signalled to the Host and not the expected TX Accept and the Host must upload the incoming packet before the TX packet can be downloaded. The TX Request should be left asserted (low) during the upload. The SP2 will respond as normal after the upload is completed.
• For the above reason it is often easier to use RX Request to trigger a HOST interrupt and upload the SP2 to the HOST under interrupt control.
• See Appendix B and C. for example SP2 driver subroutines.

2.2.2 READ A BYTE FROM THE SP2

The sequence for a byte transfer from the SP2 to the HOST (i.e. RX upload) is asynchronous and proceeds as follows :-

1. SP2 will assert RX Request line low to initiate transfer
2. Host pulls RX Accept low (i.e. request is accepted by the host)
3. SP2 will turn on it's bus drivers, place LS nibble onto data lines and negate RX Request (set to 1)
4. Host reads the data and negates RX Accept (i.e. data has been accepted)

Repeat steps 1-4 with MS nibble.

figure 7: RX upload timing diagram
Click on the image for EXPANDED VIEW

Notes:

• The SP2 will turn off it's data bus drivers after the entire packet has been uploaded to the HOST.
• See Appendix B and C. for example SP2 driver subroutines.

2.3 HOST<>SP2 PACKET FORMAT

2.3.1 THE CONTROL BYTE

The first byte of a SP2 <> HOST packet transfer is always the CONTROL BYTE. This byte is used to control the transfer and contains information about the type of packet, number of bytes to be transferred, memory address, read/write bit etc. Bit 7 of the control byte is the Packet Type flag, PT, it determines the class of transfer and the interpretation of the other bits in the control byte.

2.3.2 SENDING AND RECEIVING DATA PACKETS

Data packets are sent to / received from remote SP2's. They begin with a control byte with bit 7 cleared and may be of variable length and contain up to 60 bytes of user determined data.

figure 8: Control byte for data packet
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The remainder of the bytes in the data packet are of the users determination. The packet would usually be made up of a number of fields consisting of some but not necessarily all of the following :-

Source address / ID
Destination address / ID
System ID
Packet count
Encryption / Scrambler control
Additional error check codes ( The SP2 performs it's own error checks)
Routing information ( for repeaters)
Link control codes (connect/disconnect/ACK/NAK etc.)
Data field

2.3.3 SP2 MEMORY ACCESS

The SP2's EEPROM memory can be accessed by setting bit 7 in the control byte. Bit 6 (R/W flag) defines a memory read or write. The bits left define the address.

figure 9: SP2 memory access
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SP2 Memory READS:

Host issues just the control byte, with bit 6 (W/R) cleared, bit 7 (PT) set and the memory address. The SP2 will respond with 2 bytes, the first is a control byte which is an echo of the control byte just issued by the host, this is useful if the host is using an interrupt handler. The 2nd byte is the memory contents.

SP2 Memory WRITES:

Host issues 2 bytes, the first is the control byte with bit 6 (W/R) set, bit 7 (PT) set and the memory address. The 2nd byte is the data to be written. The SP2 does not give a response to memory writes.

figure 10: Control byte for memory access
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Notes: Memory writes to locations 01 to 3F, write to the non-volatile EEPROM in the SP2. The EEPROM has a limit of 100,000 write cycles therefor it's use must be restricted to infrequently changed data. The SP2 only writes to the EEPROM when instructed to by the HOST. Each byte takes 10ms to write. To prevent accidental/spurious writes to EEPROM the host must set the WE bit in SWITCHES prior to EACH byte to be written. We recommend that the host performs a read/verify after each byte write to EEPROM.

The above does not apply to any memory reads nor to writes to SWITCHES (address 00 H).

3.0 SP2'S SWITCHES

SWITCHES is memory location 00 in RAM, it contains 8 flags which are used to determine the SP2's operation. On SP2 reset, power-up or watchdog Time-Out it is loaded from location 08 (in EEPROM). The default value is 00 hex - this is all functions deselected.

figure 11: Switches
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3.1 PS0 & PS1 - POWER SAVING

The SP2 has 4 levels of power saving selected by PS0 & PS1 in SWITCHES. Power saving is achieved by shutting down the Transceiver and the SP2 for a period of time (OFF-TIME) when the SP2 is in the Idle state (i.e. nothing happening). During the OFF period current is reduced to the device leakage of < 50 µA typ. The SP2 will still respond immediately to a Host TX Request but cannot receive radio signals. After the programmed OFF-TIME the SP2 will wake itself up, turn the receiver on and listen for valid preamble. ON time = PWR->RX (EEPROM address 05) + 2.5ms = 3.3ms (using SP2 Default values) If preamble is found the SP2 will stay ON and decode the packet, if not the SP2 will shut down for another OFF time period.

Also see - WAKE-UP (address 02 of EEPROM) and paragraph 2.3.2.

3.3 WE - EEPROM WRITE ENABLE

This bit protects the EEPROM from accidental writes, it must be set to 1 prior to each byte write to the EEPROM (addresses 01h to 3Fh). This bit will be cleared by the SP2 after each byte write.

3.4 ST - Reserve

Do not use. Reserved for future use.

3.5 LBT & DBT - COLLISION AVOIDANCE

Listen Before Transmit, LBT, and Delay Before Transmit, DBT determine what collision avoidance the SP2 will take before each transmission.

4.0 USER CONFIGURABLE PARAMETERS IN EEPROM

The EEPROM has address range 01h - 3Fh (63 Bytes)
The first 15 BYTES (8 are defined) contain parameters used to control the SP2.

figure 12: SP2's EEPROM memory
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Address 09 to 0F are reserved for future and should not be used by the HOST

EEPROM Addresses 10 TO 3F (48 BYTES) are free for HOST use as general storage.

5.0 DIAGNOSTIC / DEBUG TEST MODES

These special test modes are useful for system testing and debugging

To select these modes the SP2 should be released from reset with the TXR line held low, normal SP2 operation will resume when the TXR is set high, i.e. TXR should be held while in these test modes.

figure 13: diagnostic mode selection timing diagram
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Note: For normal operation of the SP2 the TXR line must be held high for either 1ms after a reset pulse or 100ms after a power up.

There are 8 test modes which are selected by a binary code applied to the SP2's data bus. A 4 bit DIL switch or rotary HEX switch connected between the data bus and 0V will select the modes (the SP2 has weak internal pull-up's). Alternatively the HOST may select the test modes by holding TXR low, resetting the SP2 and driving the required test mode code onto the data bus.

Note: The SP2 continuously monitors the mode selected i.e. a reset is not required on mode changes.

In some modes the RXR output from the SP2 is driven low to indicate 'pass' or 'OK'. An LED + 1kW from RXR to 5V is recommended.

Modes 6 & 7 are particularly useful for software debugging and range testing.

figure 14: stand-alone diagnostic mode
Click on the image for EXPANDED VIEW

APPENDIX - A

A Detailed look at the SP2's transceiver interface

The SP2 interfaces to the transceiver using 4 lines :-

Note:

1. All lines are 5 volt CMOS levels
2. There is no requirement for a carrier/signal detect signal from the transceiver nor for the RXD output to be muted when no signal is present.

The enable lines - TX & RX
These normally high, active low lines are used to control the transceiver. The SP2 is a half-duplex controller thus in normal operation the transceiver is either transmitting or receiving or off.

Transmit Data - TXD
TXD is the serial data to the transmitter, it is held low when the transmitter is not enabled. When the TX is enabled a synchronous160kbit/s (6.25µs/bit) serial code is present to modulate the transmitter.

Receive Data - RXD
RXD is a hi-impedance input which is feed with a 'squared-up' (5V logic level) signal from the receivers' data slicer. The SP2 contains a very selective, noise immune signal detector and therefor does not require that the RXD signal be muted in the absence of signal, i.e.. squared-up channel noise may be fed to the SP2 when no signal is present.

The SP2's Packet Decoder

Signal Decoding is in 4 stages :-

Search
Initially the SP2's decoder searches the radio noise on the RXD line for the 80kHz preamble signal. The search is performed by a 16 times over-sampling detector which computes the spectral level of 80kHz in 192 samples of the RXD signal (156µs window). If the level exceeds a pre-set threshold the decoder will attempt to decode a packet.

Lock-in
The same set of 192 samples are used to compute the phase of the incoming preamble and synchronise the internal recovery clock to an accuracy of ±2µs. The recovery clock samples the mid point of each incoming data bit and shifts the samples trough an 8 bit serial comparator. The comparator searches the data on a bit by bit basis for the frame sync byte. While the search is in progress, the decode will abort if the preamble fails to maintain a certain level of integrity. If the comparator finds the 'please hold the line' code used during extended wake-up preamble a phase re-lock is triggered to ensure accurate phase tracking until the actual packet arrives. When the frame sync is detected the decoder attains full synchronisation and will move to the Decode state.

Decode
Data is now taken in 12 bits at a time (one symbol), decoded into the original byte and placed in the receive buffer. The symbol decoder verifies each received symbol as valid (only 256 out of a possible 4096 are valid) and will immediately abort the decode on a symbol failure. The first byte contains the byte count and is used to determine the end of message.

Check Sum
The last byte is the received check sum, this is verified against a locally generated sum of all the received bytes in the packet. If it matches the packet is valid and RXR line will be pulled low to inform the Host that a packet awaits uploading.

Notes on error handling

The SP2's' decoder is deliberately non bit error tolerant, i.e.. no attempt is made to repair corrupt data bits. All of the redundancy in the code is directed towards error checking. For an FM radio link using short packet lengths, e.g. SP2 + BiM2 , packets are either 100% or so grossly corrupt as to be unrecoverable. By the same reasoning, the Host is not informed when the SP2 decoder aborts a packet decode since corrupt information is of little value. An packet acknowledge Time-Out and re-transmission is the preferred strategy for error handling.

APPENDIX - B

Example SP2 driver subroutines for Arizona PIC16C73

figure 15: SP2 to PIC-uC interface
Click on the image for EXPANDED VIEW

Packet transfers to/from the SP2 are best handled in the host by two subroutines :- OUT_BYTE & IN_BYTE

Additionally LISTEN_BUS is called on completion of a packet transfer to the SP2 to return the data bus to inputs (default state).

APPENDIX - C

Example SP2 driver subroutines for Motorola 68HC11

figure 16: SP2 to HC11-uC interface
Click on the image for EXPANDED VIEW

Packet transfers to / from the SP2 are best handled in the host by two subroutines :- OUT_BYTE & IN_BYTE

Additionally LISTEN_BUS is called on completion of a packet transfer to the SP2 to return the data bus to inputs (default state).

APPENDIX - D

The FRPC as a control IC

Clock frequency
All timings within the SP2 (except sleep) are determined by the clock frequency. The standard frequency is 20.48MHz and all timings unless explicitly stated otherwise, assume this clock frequency.

The data rate = f_clk/128 ( i.e. 160kbps for f_clk= 20.48MHz)

Clock accuracy
The SP2 uses synchronous data transmission and requires an accurate reference clock. In the worst case, max preamble and packet length, the allowable bit rate timing error between transmitter and receiver is 0.2 bits in 1000 bits, i.e. ±200ppm total or ±100ppm at each end.

BIT TIME = 128/f_xtal (Hz) i.e. 20.48 MHz crystal = 6.25µs PER BIT

Accuracy, temp drifts MUST KEEP X-TAL ±100ppm of nominal

Limitation of liability

The information furnished by Radiometrix Ltd is believed to be accurate and reliable. Radiometrix Ltd reserves the right to make changes or improvements in the design, specification or manufacture of its subassembly products without notice. Radiometrix Ltd does not assume any liability arising from the application or use of any product or circuit described herein, nor for any infringements of patents or other rights of third parties which may result from the use of its products. This data sheet neither states nor implies warranty of any kind, including fitness for any particular application. These radio devices may be subject to radio interference and may not function as intended if interference is present. We do NOT recommend their use for life critical applications.
The Intrastat commodity code for all our modules is: 8542 6000.

R&TTE Directive

After 7 April 2001 the manufacturer can only place finished product on the market under the provisions of the R&TTE Directive. Equipment within the scope of the R&TTE Directive may demonstrate compliance to the essential requirements specified in Article 3 of the Directive, as appropriate to the particular equipment.
Further details are available on The Office of Communications (Ofcom) web site:
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